A bit-serial architecture for a multiplierless DCT

• Main Authors: Choomchuay, S., Timakul, S.
• Format: Article
• Language: English
• Published: Universiti Utara Malaysia 2003
• Subjects: QA75 Electronic computers. Computer science
• Online Access: http://repo.uum.edu.my/1019/1/S._Choomchuay.pdf; http://repo.uum.edu.my/1019/; http://jict.uum.edu.my

This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to a 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For low power applications and smaller hardware siz...