A Performance Comparison Study on Multiplier Designs
This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance d...
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my.utp.eprints.49882017-01-19T08:24:48Z A Performance Comparison Study on Multiplier Designs Lee, Chris Y. H. Lo, H. H. Lee, Sean, W. F. Hamid, Nor Hisham TK Electrical engineering. Electronics Nuclear engineering This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance data was extracted after logic synthesis in LeonardoSpectrum for Area, Speed and Auto optimization modes. Findings indicate that the Dadda multiplier may not always have a speed advantage over Wallace’s design, but depends greatly on the optimization effects in gate-level synthesized design. Results for comparison of 32x32-bit variants indicate that the Wallace scheme is well suited for high-speed applications, independent of area constraints, while the Dadda and Reduced Area designs deliver best speed when synthesized to minimize area or logic usage. 2010 Article PeerReviewed application/pdf http://eprints.utp.edu.my/4988/3/stamp.jsp%3Ftp%3D%26arnumber%3D5716117%26tag%3D1 Lee, Chris Y. H. and Lo, H. H. and Lee, Sean, W. F. and Hamid, Nor Hisham (2010) A Performance Comparison Study on Multiplier Designs. Proceedings International Conference of Intelligent and Advanced System . http://eprints.utp.edu.my/4988/ |
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TK Electrical engineering. Electronics Nuclear engineering Lee, Chris Y. H. Lo, H. H. Lee, Sean, W. F. Hamid, Nor Hisham A Performance Comparison Study on Multiplier Designs |
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This study investigates the relative performances of Array,
Wallace, Dadda and Reduced Area multipliers for several
synthesis optimization modes. All multiplier designs were
modeled in Verilog HDL and synthesized based on the
TSMC 0.35-micron ASIC Design Kit standard cell library.
Performance data was extracted after logic synthesis in
LeonardoSpectrum for Area, Speed and Auto optimization
modes. Findings indicate that the Dadda multiplier may not
always have a speed advantage over Wallace’s design, but
depends greatly on the optimization effects in gate-level
synthesized design. Results for comparison of 32x32-bit
variants indicate that the Wallace scheme is well suited for
high-speed applications, independent of area constraints,
while the Dadda and Reduced Area designs deliver best
speed when synthesized to minimize area or logic usage. |
format |
Article |
author |
Lee, Chris Y. H. Lo, H. H. Lee, Sean, W. F. Hamid, Nor Hisham |
author_facet |
Lee, Chris Y. H. Lo, H. H. Lee, Sean, W. F. Hamid, Nor Hisham |
author_sort |
Lee, Chris Y. H. |
title |
A Performance Comparison Study on Multiplier Designs |
title_short |
A Performance Comparison Study on Multiplier Designs |
title_full |
A Performance Comparison Study on Multiplier Designs |
title_fullStr |
A Performance Comparison Study on Multiplier Designs |
title_full_unstemmed |
A Performance Comparison Study on Multiplier Designs |
title_sort |
performance comparison study on multiplier designs |
publishDate |
2010 |
url |
http://eprints.utp.edu.my/4988/3/stamp.jsp%3Ftp%3D%26arnumber%3D5716117%26tag%3D1 http://eprints.utp.edu.my/4988/ |
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1738655381182218240 |
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13.18916 |