Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits

• Main Authors: Zahoor, F., Zulkifli, T.Z.A., Khanday, F.A., Zainol Murad, S.A.
• Format: Article
• Published: Institute of Electrical and Electronics Engineers Inc. 2020
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85086734536&doi=10.1109%2fACCESS.2020.2997809&partnerID=40&md5=6a618c37868f1dc0b1c2d2786f6c0ff1; http://eprints.utp.edu.my/23325/

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50 in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11 reduction in transistor count is observed while for TM design, around 38 reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations. © 2013 IEEE.