A 16×2 geiger mode photon counter array automated data acquisition systems in 0.18 μm CMOS Process

• Main Author: Chong, Yok Kian
• Format: Thesis
• Language: English
• Published: 2022
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/99384/1/ChongYokKianMSKE2022.pdf; http://eprints.utm.my/id/eprint/99384/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149998

Photon detection technology involving single photon detection and counting is vital for areas such as biomedical, agriculture, two-dimensional imaging, three-dimensional ranging and fluorescence correlation spectroscopy. These applications require a photon detection system with fast response time and high sensitivity and Single Photon Avalanche Diode (SPAD) is identified to be a suitable candidate as a photon detector. SPAD provides fast photon counting, low biasing voltage, small in size and ability to integrate with Complementary Metal-Oxide Semiconductors (CMOS) compared with other photon detection methods. The motivation of this project is to achieve physical implementation of 2-Dimensional Array of SPAD with intention of improving sensitivity. Previous studies show limitations of SPAD application to detect very low intensity photon signals due to insufficient sensitivity. This project suggests a robust data acquisition system to work with 16 x 2 photon counting array of SPAD detector and its readout controller module. The integrated circuit will be implemented in Verilog Hardware Descriptive Language (HDL), simulated, synthesized, and tested for Application Specific Integrated Circuit (ASIC) implementation using Synopsys Electronic Design Automation (EDA) tool. Besides that, an additional task is in place to realize fabrication ready physical implementation of the proposed integrated circuit using 0.18 μm CMOS technology. The full design consists of 16 x 2 SPAD model, 16 bits 2 to 1 multiplexer, Brent-Kung Adder (BKA) as data acquisition system and a Parallel In Parallel Out (PIPO) shift register. Verifications are done to each element individually and to whole system to ensure functionality correctness. Physical implementation of the whole system is carried out to study area and power performance of the post-layout design. The 16 x 2 BKA system is able to achieve an area reduction of 20.93 % when taking the 16 x 2 KSA system as reference. The maximum main clock frequency and area consumption achieved by the 16 x 2 BKA system are 680.3 MHz and 11688.97 μm2 respectively.