Asymmetrical multilevel inverter topology with reduced power semiconductor devices

• Main Authors: Arif, M. Saad, Md. Ayob, Shahrin, Salam, Zainal
• Format: Conference or Workshop Item
• Published: 2017
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/97212/; http://dx.doi.org/10.1109/IEACON.2016.8067349

In this paper, a new single-phase asymmetrical multilevel inverter topology is proposed. The topology is capable of producing n-level output voltage with reduced device counts. It is achieved by arranging available switches and dc sources to obtain maximum combinations of addition and subtraction of the input dc sources. To verify the viability of the proposed topology, circuit models for nine-level, 25-level and 67-level inverter are developed and simulated in Matlab-Simulink software. Experimental results of the proposed nine-level inverter prototype, developed in the laboratory, are presented. A low frequency switching strategy for nine-level inverter is also presented in this work. Comparison between the existing multilevel topologies shows that the proposed circuit requires less number of power switches and dc sources to produce the same number of output level.