A survey on network on chip routing algorithms criteria
As number of components on the semi-conductor industry is growing at a healthy rate, results in an increase in number of cores integrating on a chip. Demand for core interconnections brings network on chip (NoC) under consideration. Instead of using traditional on chip interconnection, NoC is proved...
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| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Published: |
2020
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/94158/ http://dx.doi.org/10.1007/978-981-15-6048-4_40 |
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| Summary: | As number of components on the semi-conductor industry is growing at a healthy rate, results in an increase in number of cores integrating on a chip. Demand for core interconnections brings network on chip (NoC) under consideration. Instead of using traditional on chip interconnection, NoC is proved to be a promising solution. Communicating nodes require routing algorithm for successful transmission of packets. In this paper, we highlight the recent challenges of routing algorithms and classification of routing algorithm techniques in different criteria such as aging-aware, thermal-aware, congestion-aware, fault-aware, resilient, and energy efficient. It was challenging to design a NoC routing algorithm capable of providing less congested paths, better energy efficiency, and high scalability. Now, it is even more challenging to design routing algorithm to deal with other issues such as aging of network, hotspot in the network due to high temperature, high temperatures can produce faults in the system, enhance power efficiency and resilient to enhance tolerance. Routing algorithm has a significant impact on latency and throughput of network on chip. In the end, we discussed performance matrices commonly used for evaluation of NoC routing algorithms. To the best of our knowledge, this is the only study which is focusing on modern criteria of NoC routing algorithms. |
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