Asic design for healthiness recognition of agriculture

• Main Author: Chin, Linn Kern
• Format: Thesis
• Language: English
• Published: 2020
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/93000/1/ChinLinnKernMSKE2020.pdf; http://eprints.utm.my/id/eprint/93000/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135893

The purpose of this study is to develop the application of healthiness recognition of agriculture plant module and then develop the module into ASIC design. Plant disease is a common issue which leads to decrease in the food production in the crop agriculture sector. The main factor of plant disease is caused by microorganism which include bacteria, fungi and virus. Nitrogen play an important role in the yield of plant. Excess of or lacking in nitrogen may affect the deficiency in crop. There are few methods for nitrogen detection in the leaf such as colour analysis using image processing, remote sensing and neural network etc. In this project, HSV colour model is used for colour analysis through image processing that able to separate the colour portion from the intensity. Before the colour analysis, median filter is used as pre-processing step to remove unwanted salt and pepper noise in the image and preserver the edge of the leaf in the image. After pre-processing step and colour, linear SVM classification is used as classification step. Linear SVM classification, able to classify the plant into healthy and unhealthy categories by determine the concentration of nitrogen in the leaf with 95.36 % accuracy. The algorithm of recognition module is verified through Matlab software simulation. After that, HLS is used to translate the high-level language into hardware description language. The tool can handle complex image processing algorithm and floating point in the algorithm. Unrolled factor for for-loop and pipeline is combined and implemented into the design to obtain the best hardware utilization resource and timing result at netlist level. Lastly, the Verilog netlist of image recognition system is implemented into ASIC. The benefit of ASIC design, that is closer to hardware descript language, and able to minimize the latency and increase the efficiency. ASIC design has been produced successfully with 24.2 mW of power consumption, 0.039 mm2 area and able to operate at 250 MHz clock frequency.