Electrocardiogram QRS detection hardware accelerator for ASIC implementation

• Main Author: Lim, Zhi Qing
• Format: Thesis
• Language: English
• Published: 2020
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/92993/1/LimZhiQingMSKE2020.pdf; http://eprints.utm.my/id/eprint/92993/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135892

Electrocardiogram (ECG) analysis is an important tool to detect the heart pulse rate and rhythm. QRS complex plays a vital role in such analysis. This work presents ECG QRS detection based on Pan-Tompkins algorithm using 90nm ASIC design architecture. Among plenty of QRS detection algorithm, Pan-Tompkins algorithm is chosen to detect QRS complex in ECG signal due to its simplicity and accuracy in detecting QRS complex. The algorithm is modified to use together with adaptive threshold for R-peak detection. The input of ASIC design is Hardware Description Language (HDL) code. Nevertheless, compute intensive algorithm and complexity in building Hardware Description Language can degrade timing performance of design which can lead to life-threatening impact to patient. Through this project, a hardware accelerator of QRS complex detector is designed with Register Transfer Level (RTL) optimization technique to improve the timing performance. Before RTL code is developed, the algorithm is modelled in MATLAB to confirm its functionality. To maximize design space exploration and minimize design time due to HDL complexity on building an algorithm, VIVADO HLS tool is introduced in this project. Loop unrolling and loop pipelining technique are used to optimize hardware code in VIVADO HLS. Analysis on design latency, resource utilization, accuracy and total execution time with respect to software baseline is conducted. At the end of the project, total double speedup is achieved, and 144455 cycles are reduced after optimization is done in hardware code. However, number of FF is increased by 30% from original number while the number of LUT is increased by 17% from the original number. On ASIC design analysis, total area and power consumption are found to be 1.686mm2 and 9.78mW respectively. From Synopsys Prime Time result, the setup time and hold time of the design are met.