Test register insertion at RTL based on reduced BIST

• Main Authors: Paraman, N., Ooi, C. Y., Sha'ameri, A. Z., Fujiwara, H.
• Format: Article
• Published: Penerbit UTM Press 2017
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/76734/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-85008217112&doi=10.11113%2fjt.v79.8479&partnerID=40&md5=2f973c045c17e3ab5bb5e3694723fd20

Built-in self-test (BIST) method has high area overhead and long test application time. In this paper, a new BIST method is proposed at register transfer level (RTL) as a design for testability (DFT) method to modify a given RTL circuit to a reduced BISTable RTL circuit. First, we introduce modellin...