A novel scan architecture for low power scan-based testing
Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introd...
Saved in:
Main Authors: | , |
---|---|
Format: | Article |
Published: |
Hindawi Publishing Corporation
2015
|
Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/55787/ http://dx.doi.org/10.1155/2015/264071 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|