A novel scan architecture for low power scan-based testing
Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introd...
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| Main Authors: | , |
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| Format: | Article |
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Hindawi Publishing Corporation
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/55787/ http://dx.doi.org/10.1155/2015/264071 |
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