Hardware and software co-simulation platform for convolution or correlation based image processing algorithms

• Main Author: Ayat, Sayed Omid
• Format: Thesis
• Language: English
• Published: 2014
• Subjects: TK7885-7895 Computer engineer. Computer hardware
• Online Access: http://eprints.utm.my/id/eprint/48734/25/SayedOmidAyatMFKE2014.pdf; http://eprints.utm.my/id/eprint/48734/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:85686

Software implementation of image processing algorithms in which convolution or correlation is applied is too slow to be real-time. As long as the system design gets larger, it should be partitioned into two parts: software and hardware. In order to achieve real time performance, it is essential to map the fast convolution or correlation module, which is the heaviest computation intensive part, in hardware instead of software. Our test case is “generic image pre-processing algorithm” which includes resizing, noise filtering and normalization. In noise filtering part of the preprocessing algorithm in which convolution is used should be implemented in hardware while the rest of the preprocessing algorithm stays in software. Next, to verify our hardware/design software we can deploy it on FPGA board, but it is very time consuming and involves a lot of technical complexities. In that case, this design used hardware/software co-simulation and direct programming interface (DPI-C) whereas it allows System Verilog calls C functions and vice versa. The proposed work has overcome the problems faced when running a co-simulation based on Modelsim simulated using direct programming interface (DPI) technique.