Software-based self-testing for a risc processor
Software-based self-testing (SBST) has been touted as the effective way to test the processors effectively, with reasonable test coverage, plus the advantages of at-speed testing, and without performance degradation in terms of area and power. Previous work has been done on combining SBST with parti...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2014
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/48617/1/TehWeeMengMFKE2014.pdf http://eprints.utm.my/id/eprint/48617/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:82137?queryType=vitalDismax&query=Software-based+self-testing+for+a+risc+processor&public=true |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Software-based self-testing (SBST) has been touted as the effective way to test the processors effectively, with reasonable test coverage, plus the advantages of at-speed testing, and without performance degradation in terms of area and power. Previous work has been done on combining SBST with partial scan logic insertion at Register Transfer Language (RTL) level for a 16-bit RISC processor design. In this project, focus will be done on test coverage improvement without the use of scan logic. |
|---|