Second-stage tuning procedure for analogue CMOS design reuse methodology

• Main Authors: Adnan, A. F. B., A'ain, Abu Khairi, Marsono, Muhammad Nadzir, Kamisan, I. B., Grout, I. A.
• Format: Article
• Published: The Institution of Engineering and Technology 2012
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/33500/; https://ieeexplore.ieee.org/document/6260051

Proposed is a two-stage analogue circuit design reuse methodology by extending existing fabrication process rescaling procedures with a follow-on systematic tuning procedure stage based on DC output voltage scaling. It increases the potential for design reuse with short-channel MOSFET circuit design...