Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm

• Main Authors: Chia, Yee Ooi, Jia, Pao Sua, Siaw, Chen Lee
• Format: Article
• Published: Elsevier 2012
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/33467/; http://dx.doi.org/10.1016/j.compeleceng.2012.04.010

The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Re...