Designing memory cells with a novel approaches based on a new multiplexer in QCA Technology

• Main Author: Majeed, Ali Hussien
• Format: Thesis
• Language: English; English; English
• Published: 2022
• Subjects: T Technology (General)
• Online Access: http://eprints.uthm.edu.my/8390/1/24p%20ALI%20HUSSIEN%20MAJEED.pdf; http://eprints.uthm.edu.my/8390/2/ALI%20HUSSIEN%20MAJEED%20COPYRIGHT%20DECLARATION.pdf; http://eprints.uthm.edu.my/8390/3/ALI%20HUSSIEN%20MAJEED%20WATERMARK.pdf; http://eprints.uthm.edu.my/8390/

Transistor-based CMOS technology has many drawbacks such that it cannot continue to follow the scaling of Moore’s law in the near future. These drawbacks lead researchers to think about alternatives. Quantum-dot Cellular Automata (QCA) is a nanotechnology that has unique features in terms of size and power consumption. QCA has the ability to represent binary numbers by electrons configuration. The memory circuit is a very important part of the digital system. In QCA technology, there are many approaches presented to accomplish memory cells in both RAM and CAM types. CAM is a type of memory used in high-speed applications. In this thesis, novel approaches to design memory cells are proposed. The proposed approaches are based on a 2:1 multiplexer. Using the proposed approach of RAM cell, a singular form of RAM cell (SFRAMC) is accomplished. In QCA technology, researchers strive to design electronic circuits with an emphasis on minimizing important metrics such as cell count, area, delay, cost and power consumption. The SFRAMC demonstrated significant improvements, with a reduction cell count, occupied area and power consumption by 25%, 24% and 36%. In terms of implementation cost, the SFRAMC saves 43% of the cost when compared to the previous best design. On the other hand, by using the proposed approach of CAM cell, two different structures of the QCA-CAM cell have been introduced. The first proposed CAM cell (FPCAMC) gives improvements in terms of cell count, and delay by 15% and 17% respectively. The second proposed CAM cell (SPCAMC) gives improvements in terms of cell count, and delay by 6% and 17% respectively. In terms of total power consumption, both FPCAMC and SPCAMC have an improvement of about 53% over the best-reported design. The above features of the proposed memory cells (RAM and CAM) could pave the road for designing energy-efficient and cost-efficient memory circuits in the future.