An optimum design of a two-stage operational amplifier using carbon nanotube field-effect transistor at 10 nm technology node

• Main Author: Chua, Wee Heng
• Format: Thesis
• Language: English; English; English
• Published: 2022
• Subjects: T Technology (General)
• Online Access: http://eprints.uthm.edu.my/8257/1/24p%20CHUA%20WEE%20HENG.pdf; http://eprints.uthm.edu.my/8257/2/CHUA%20WEE%20HENG%20COPYRIGHT%20DECLARATION.pdf; http://eprints.uthm.edu.my/8257/3/CHUA%20WEE%20HENG%20WATERMARK.pdf; http://eprints.uthm.edu.my/8257/

The shrinking of the metal oxide semiconductor field-effect transistor (MOSFET) technology nodes to the deep-nanometre size leads to serious short-channel effects. Among the various technologies and device structures that have been proposed, the carbon nanotube field-effect transistor (CNFET) is the most promising candidate to replace the MOSFET. The effect of the structural parameters of CNFET on the two-stage operational amplifier (op-amp) performance is one of the active research areas in studying the CNFET when scaling down the CNFET based circuit from a larger technology node to a smaller technology node. This research investigates the CNFET structural parameters which are the number of tubes (N), the carbon nanotube (CNT) diameter (DCNT), and the CNT pitch (S) to optimize the design of 32 nm and 10 nm two-stage CNFET op-amps. The op-amp circuits are optimized by balancing the open-loop gain, unity-gain bandwidth (UGB), power dissipation, and output resistance to obtain the optimum structural parameters. The optimized 10 nm two-stage op-amp is then compared with 32 nm to evaluate the optimum structural parameters and circuit performances. The evaluated circuit performances consist of open-loop gain, UGB, power dissipation, output resistance, input common-mode range (ICMR), common-mode rejection ratio (CMRR), power-supply rejection ratio (PSRR), slew rate, and settling time. Furthermore, this research also investigates the effect of S on the CNFET drain current (ICNFET) when migrating from 32 nm to 10 nm technology node. Simulation results show that the optimum design of the 10 nm two-stage op-amp has successfully improved the performance of the 32 nm circuit by more than 33% for all the performance metrics. The performance metric that improved the most is UGB, which increased by 109.99%. The investigation of the impact of S on the ICNFET when the size of the CNFET is reduced to 10 nm technology node suggests that the S parameter should be taken into account in the 32 nm ICNFET equation for accurate drain current estimation. On the other hand, for simplicity, S can be neglected in the 10 nm ICNFET equation without sacrificing accuracy.