Single-switch bridgeless PFC sepic with proposed series-line-diodes-clamped configuration for data communication applications

• Main Author: Romai Noor, Mohd Kamil
• Format: Thesis
• Language: English; English; English
• Published: 2019
• Subjects: TK5101-6720 Telecommunication. Including telegraphy, telephone, radio, radar, television
• Online Access: http://eprints.uthm.edu.my/568/1/24p%20MOHD%20KAMIL%20ROMAI%20NOOR.pdf; http://eprints.uthm.edu.my/568/2/MOHD%20KAMIL%20ROMAI%20NOOR%20COPYRIGHT%20DECLARATION.pdf; http://eprints.uthm.edu.my/568/3/MOHD%20KAMIL%20ROMAI%20NOOR%20WATERMARK.pdf; http://eprints.uthm.edu.my/568/

This research presents a Single-Switch Bridgeless PFC (SSBPFC) SEPIC which is passive PFC with proposed series-line-diodes-clamped (SLDC) configuration for circuit structure simplicity and power quality issues mitigation. The structure simplification considers the reduction in number of components, while the power quality issues considers the parameters design of components. Basically, the BPFC SEPIC consists of more number of components and has the possibility of having power quality issues due to the combination of two operation circuits in one converter. When the BPFC SEPIC was implemented, several major drawbacks exist such as circulating current, capacitive coupling loop, more current stress at input capacitors and line-diodes, high total harmonic distortion of current (THDi), low power factor, dead zones, and high output voltage ripple. Therefore, a SSBPFC SEPIC structure with SLDC configuration was presented to solve the major drawbacks of the previous BPFC SEPIC. The principle employed for optimisation of parameters design was based on the energy balancing compensation between the input capacitors and output inductors to reduce the THDi. Besides, the input and output inductors were designed to operate in DCM and CCM respectively based on the ripple balancing concept to improve the quality of AC source. A large value of output capacitor was used to reduce the output voltage ripple. The simulation and experimental results showed a good agreement with the proposed designed parameters. The experimental results demonstrated that the THDi was reduced from 56.2% to 4.7% after optimisation and the dead zones were inherently eliminated. It was confirmed that the output voltage ripple frequency was always double from the line frequency, 50 Hz and the output voltage ripple was reduced from 19 V to 7 V and consequently produced a constant DC output voltage. The circulating current and capacitive coupling loop were eliminated, causing the maximum current stress at line-diodes and input capacitor to be reduced. Therefore, the design of the proposed converter was confirmed with approximately 100 W of the output power.