Evaluation of high power density achievement of optimum 4-level capacitor-clamped DC–DC boost converter with passive lossless snubber circuit by using Pareto-Front method

• Main Authors: Naim Kasiran, Mohd Amirul, Ponniran, Asmarashid, Yatim, Mohd Hafizie, Itoh, Jun-ichi
• 格式: Article
• 語言: English
• 出版: Institution of Engineering and Technology (IET) 2020
• 主題: T Technology (General); TK7800-8360 Electronics
• 在線閱讀: http://eprints.uthm.edu.my/4976/1/AJ%202020%20%2856%29.pdf; http://eprints.uthm.edu.my/4976/; https://dx.doi.org/ 10.1049/iet-pel.2019.0604

This study presents the evaluation of the proposed optimum 4-level capacitor-clamped DC–DC boost converter (CCBC) for high power density achievement by using Pareto-Front method. The 4-level CCBC with considering high switching frequency can greatly reduce the inductor size and volume. High switching frequency caused the switching devices to suffer high semiconductor losses. Consequently, the cooling device volume is increased as well. Thus, this study presents softswitching technique in the 4-level CCBC for semiconductor losses reduction. The combination of optimum design of inductor, improvement of circuit structure and soft-switching technique may lead to the highest power density of the converter. A 400 W of the 4-level CCBC converter is designed and experimentally verified. The results show that the inductance and inductor volume required in the 4-level CCBC is reduced by 88.89 and 80.75%, respectively. Besides, Pareto-Front curve shows the highest power density of soft-switching technique with the proposed 4-level CCBC is 6.51 kW/dm3 at 800 kHz of switching frequency with efficiency of 97.20%.