Secure lightweight obfuscated delay-based physical unclonable function design on FPGA

• Main Authors: Mispan, Mohd Syafiq, Wong, Yan Chiew, Kamarudin, Muhammad Raihaan, Ishak, Mohammad Haziq, Korobkov, Mikhail Aleksandrovich
• Format: Article
• Language: English
• Published: Institute of Advanced Engineering and Science 2022
• Online Access: http://eprints.utem.edu.my/id/eprint/26505/2/2022_SECURE%20LIGHTWEIGHT%20OBFUSCATED%20DELAY-BASED%20PHYSICALUNCLONABLE%20FUNCTION%20DESIGN%20ON%20FPGA.PDF; http://eprints.utem.edu.my/id/eprint/26505/; https://beei.org/index.php/EEI/article/view/3265/2585

The internet of things (IoT) describes the network of physical objects equipped with sensors and other technologies to exchange data with other devices over the Internet. Due to its inherent flexibility, field-programmable gate array (FPGA) has become a viable platform for IoT development. However, various security threats such as FPGA bitstream cloning and intellectual property (IP) piracy have become a major concern for this device. Physical unclonable function (PUF) is a promising hardware finger-printing technology to solve the above problems. Several PUFs have been proposed, including the implementation of reconfigurable-XOR PUF (R-XOR PUF) and multi-PUF (MPUF) on the FPGA. However, these proposed PUFs have drawbacks, such as high delay imbalances caused by routing constraints. Therefore, in this study, we explore relative placement method to implement the symmetric routing in the obfuscated delay- based PUF on the FPGA board. The delay analysis result proves that our methodto implement the symmetric routing was successful. Therefore, our work has achieved good PUF quality with uniqueness of 48.75%, reliability of 99.99%, and uniformity of 52.5%. Moreover, by using the obfuscation method, which is an Arbiter-PUF combined with a random challenge permutation technique, we reduced the vulnerability of Arbiter-PUF against machine learning attacks to 44.50%.