Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA

In recent years the Space Vector Modulation (SVM) technique has gained wide acceptance for many AC drive applications. Further improvements of AC drives can be accomplished by applying SVM in multilevel inverters, since the more suitable voltage vectors can be chosen among larger number of voltage v...

Full description

Saved in:
Bibliographic Details
Main Author: Al-Jewari, Maher Abd Ibrahim
Format: Thesis
Language:English
English
Published: 2019
Subjects:
Online Access:http://eprints.utem.edu.my/id/eprint/25512/1/Implementation%20Of%20SVM%20For%20Cascaded%20H-Bridge%20Multilevel%20Inverters%20Utilizing%20FPGA.pdf
http://eprints.utem.edu.my/id/eprint/25512/2/Implementation%20Of%20SVM%20For%20Cascaded%20H-Bridge%20Multilevel%20Inverters%20Utilizing%20FPGA.pdf
http://eprints.utem.edu.my/id/eprint/25512/
https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=117869
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.utem.eprints.25512
record_format eprints
spelling my.utem.eprints.255122022-01-06T12:03:27Z http://eprints.utem.edu.my/id/eprint/25512/ Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA Al-Jewari, Maher Abd Ibrahim T Technology (General) TK Electrical engineering. Electronics Nuclear engineering In recent years the Space Vector Modulation (SVM) technique has gained wide acceptance for many AC drive applications. Further improvements of AC drives can be accomplished by applying SVM in multilevel inverters, since the more suitable voltage vectors can be chosen among larger number of voltage vectors available in the multileve inverter. However, the use of multilevel inverters associated with SVM by using Digital Signal Processor (DSP) increases the complexity of control algorithm or computational burden and hence produces larger value of sampling time. This thesis reports the implementation of SVM in Cascaded H-Bridge Multilevel Inverter (CHMI) using Field Programmable Gate Arrays (FPGA) and analysis in-depth the performances of SVM computation on THD and fundamental component of output voltage. The SVM modulator is modelled using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 us. The data of switching signals for driving Insulated Gate Bipolar Transistors (IGBTSs) which are stored in MATLAB workspacs, are then used to be programmed in FPGA using a Quartus 11 software. Note that the generation of switching signals performed by FPGA is at the same sampling time in MATLAB. Using this approach, the computational burden of SVM can be greatly minimized and the desired output voltage can be obtained at high degree of accuracy. The simulation and experiment results are carried out to highlight at the advantages of using SVM and to verify the improvements of this approach by using FPGA controller. Some simulations and experiments were carried out to highlight the improvements, which are as follows; 1) the lower THD of the simulation result is about 14.37% for five-level CHMI and experiment result is about 14.35% for five- level CHMI at modulation index M; = 0.9, 2) the error percentage between the simulation and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %, where the minimum error in two-level at M; = 0.9 is around 0.06% and the maximum error in five-level at M; = 0.3 is around 0.52%. The main benefit of this approach s to provide a high precision space vector modulator for cascaded Hbridge multilevel inverter for electric vehicle and Uninterruptible Power Supply (UPS) applications. 2019 Thesis NonPeerReviewed text en http://eprints.utem.edu.my/id/eprint/25512/1/Implementation%20Of%20SVM%20For%20Cascaded%20H-Bridge%20Multilevel%20Inverters%20Utilizing%20FPGA.pdf text en http://eprints.utem.edu.my/id/eprint/25512/2/Implementation%20Of%20SVM%20For%20Cascaded%20H-Bridge%20Multilevel%20Inverters%20Utilizing%20FPGA.pdf Al-Jewari, Maher Abd Ibrahim (2019) Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA. Masters thesis, Universiti Teknikal Malaysia Melaka. https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=117869
institution Universiti Teknikal Malaysia Melaka
building UTEM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknikal Malaysia Melaka
content_source UTEM Institutional Repository
url_provider http://eprints.utem.edu.my/
language English
English
topic T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
spellingShingle T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
Al-Jewari, Maher Abd Ibrahim
Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA
description In recent years the Space Vector Modulation (SVM) technique has gained wide acceptance for many AC drive applications. Further improvements of AC drives can be accomplished by applying SVM in multilevel inverters, since the more suitable voltage vectors can be chosen among larger number of voltage vectors available in the multileve inverter. However, the use of multilevel inverters associated with SVM by using Digital Signal Processor (DSP) increases the complexity of control algorithm or computational burden and hence produces larger value of sampling time. This thesis reports the implementation of SVM in Cascaded H-Bridge Multilevel Inverter (CHMI) using Field Programmable Gate Arrays (FPGA) and analysis in-depth the performances of SVM computation on THD and fundamental component of output voltage. The SVM modulator is modelled using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 us. The data of switching signals for driving Insulated Gate Bipolar Transistors (IGBTSs) which are stored in MATLAB workspacs, are then used to be programmed in FPGA using a Quartus 11 software. Note that the generation of switching signals performed by FPGA is at the same sampling time in MATLAB. Using this approach, the computational burden of SVM can be greatly minimized and the desired output voltage can be obtained at high degree of accuracy. The simulation and experiment results are carried out to highlight at the advantages of using SVM and to verify the improvements of this approach by using FPGA controller. Some simulations and experiments were carried out to highlight the improvements, which are as follows; 1) the lower THD of the simulation result is about 14.37% for five-level CHMI and experiment result is about 14.35% for five- level CHMI at modulation index M; = 0.9, 2) the error percentage between the simulation and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %, where the minimum error in two-level at M; = 0.9 is around 0.06% and the maximum error in five-level at M; = 0.3 is around 0.52%. The main benefit of this approach s to provide a high precision space vector modulator for cascaded Hbridge multilevel inverter for electric vehicle and Uninterruptible Power Supply (UPS) applications.
format Thesis
author Al-Jewari, Maher Abd Ibrahim
author_facet Al-Jewari, Maher Abd Ibrahim
author_sort Al-Jewari, Maher Abd Ibrahim
title Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA
title_short Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA
title_full Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA
title_fullStr Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA
title_full_unstemmed Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA
title_sort implementation of svm for cascaded h-bridge multilevel inverters utilizing fpga
publishDate 2019
url http://eprints.utem.edu.my/id/eprint/25512/1/Implementation%20Of%20SVM%20For%20Cascaded%20H-Bridge%20Multilevel%20Inverters%20Utilizing%20FPGA.pdf
http://eprints.utem.edu.my/id/eprint/25512/2/Implementation%20Of%20SVM%20For%20Cascaded%20H-Bridge%20Multilevel%20Inverters%20Utilizing%20FPGA.pdf
http://eprints.utem.edu.my/id/eprint/25512/
https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=117869
_version_ 1724077898726375424
score 13.160551