Remote global alignment error for cycle time improvement of pad inductor layer

• Main Author: Devadas, Saandilian
• Format: Thesis
• Language: English; English
• Published: 2018
• Subjects: T Technology (General); TS Manufactures
• Online Access: http://eprints.utem.edu.my/id/eprint/23781/1/Remote%20Global%20Alignment%20Error%20For%20Cycle%20Time%20Improvement%20Of%20Pad%20Inductor%20Layer.pdf; http://eprints.utem.edu.my/id/eprint/23781/2/Remote%20global%20alignment%20error%20for%20cycle%20time%20improvement%20of%20pad%20inductor%20layer.pdf; http://eprints.utem.edu.my/id/eprint/23781/; http://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=112889

Lithography is the key process which transfers the pattern from mask (reticle) to wafer; and pad inductor layer is the last layer in photo masking. The cycle time for pad inductor layer has increased in Silterra Malaysia Sdn. Bhd., by 32% per month due to Global Alignment (GA) error. Meanwhile, engineering team taking long duration during troubleshooting of the lot at exposure and developing step. This is due to tool time constrain which requires a Process Engineer to perform this activity manually. Most of the lots undergo rework step which results in cost of per wafer to increase. The goal of this project is to reduce the cycle time for pad inductor layers by introducing "Remote Global Alignment Error" (RGAE) framework; in which this new framework will results in alternative flow. The methodology was designed if encountering global alignment error. During the process, the lot will automatically load in by "Remote Global Alignment Error''(RGAE) framework by selecting the rejected wafers going for exposure and developing process. This has eventually save more time for split wafers which will usually send for rework or run the lot manually. Few DOE test was conducted to compare the cycle time performance of the (RGAE) framework with the Manual Global Alignment (MGA) method. Furthermore, there main photolithography process (coat, exposure, develop),reject wafers and rework rate cycle time performance was also tested. In total, five test lots and five production lots selected to run the DOE test. All the cycle time data which was collected through this DOE test analyzed using Minitab 17 statistical software. The analyzed report shows that the cycle time for RGAE method could be achieved within 2 hours. This success could be achieved by allowing the rejected wafers to run automatically by using the alternative flow until the wafers successfully exposed. Furthermore, with the (RGAE) framework, the production can save time for split, rework, remask and merge all the wafers. The experimental result shows that (RGAE)framework able to provide fast solution by achieving 97% reduction of cycle time for pad inductor layer comparing to Manual Global Alignment (MGA) method.