Cover Image

An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm

Combinatorial logic circuit minimization is usually done using Karnaugh’s Map or Boolean equation. This paper presents an application of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is bench...

Full description

Saved in:
Bibliographic Details
Main Authors: Zainodin, Aznilinda, Ab. Kadir, Aida Khairunnisaa, Ayob, M Nasir, Hassan, Ahmad Fariz, Zainal Abidin, Amar Faiz, Zahid, Fazlinashatul Suhaidah, Jaafar, Hazriq Izzuan, Mohd Khairuddin, Ismail
Format: Conference or Workshop Item
Language:English
Published: 2014
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utem.edu.my/id/eprint/13783/1/004_CRUSC-17-21.pdf
http://eprints.utem.edu.my/id/eprint/13783/
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.utem.eprints.13783
record_format eprints
spelling my.utem.eprints.137832015-05-28T04:34:08Z http://eprints.utem.edu.my/id/eprint/13783/ An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm Zainodin, Aznilinda Ab. Kadir, Aida Khairunnisaa Ayob, M Nasir Hassan, Ahmad Fariz Zainal Abidin, Amar Faiz Zahid, Fazlinashatul Suhaidah Jaafar, Hazriq Izzuan Mohd Khairuddin, Ismail TK Electrical engineering. Electronics Nuclear engineering Combinatorial logic circuit minimization is usually done using Karnaugh’s Map or Boolean equation. This paper presents an application of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial logic circuit minimization. 2014-11-20 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utem.edu.my/id/eprint/13783/1/004_CRUSC-17-21.pdf Zainodin, Aznilinda and Ab. Kadir, Aida Khairunnisaa and Ayob, M Nasir and Hassan, Ahmad Fariz and Zainal Abidin, Amar Faiz and Zahid, Fazlinashatul Suhaidah and Jaafar, Hazriq Izzuan and Mohd Khairuddin, Ismail (2014) An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm. In: Colloquium on Robotics, Unmanned Systems And Cybernetics 2014 (CRUSC 2014), 20 November 2014, Universiti Malaysia Pahang, Pekan, Pahang, Malaysia.
institution Universiti Teknikal Malaysia Melaka
building UTEM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknikal Malaysia Melaka
content_source UTEM Institutional Repository
url_provider http://eprints.utem.edu.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Zainodin, Aznilinda
Ab. Kadir, Aida Khairunnisaa
Ayob, M Nasir
Hassan, Ahmad Fariz
Zainal Abidin, Amar Faiz
Zahid, Fazlinashatul Suhaidah
Jaafar, Hazriq Izzuan
Mohd Khairuddin, Ismail
An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
description Combinatorial logic circuit minimization is usually done using Karnaugh’s Map or Boolean equation. This paper presents an application of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial logic circuit minimization.
format Conference or Workshop Item
author Zainodin, Aznilinda
Ab. Kadir, Aida Khairunnisaa
Ayob, M Nasir
Hassan, Ahmad Fariz
Zainal Abidin, Amar Faiz
Zahid, Fazlinashatul Suhaidah
Jaafar, Hazriq Izzuan
Mohd Khairuddin, Ismail
author_facet Zainodin, Aznilinda
Ab. Kadir, Aida Khairunnisaa
Ayob, M Nasir
Hassan, Ahmad Fariz
Zainal Abidin, Amar Faiz
Zahid, Fazlinashatul Suhaidah
Jaafar, Hazriq Izzuan
Mohd Khairuddin, Ismail
author_sort Zainodin, Aznilinda
title An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_short An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_full An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_fullStr An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_full_unstemmed An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_sort experimental study of combinational logic circuit minimization using firefly algorithm
publishDate 2014
url http://eprints.utem.edu.my/id/eprint/13783/1/004_CRUSC-17-21.pdf
http://eprints.utem.edu.my/id/eprint/13783/
_version_ 1665905561703546880
score 13.211869

Similar Items