Design Of FPGA-Based Encryption Chipusing Blowfish Algorithm
Nowadays, the world has changed so rapidly that everything has become digitized and computerized. Unfortunately, digital information is very easy to be duplicated, modified, transmitted or used by unauthorized users. This results a serious problem and in view of this, some sort of security mechani...
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| Format: | Monograph |
| Language: | English |
| Published: |
Universiti Sains Malaysia
2006
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| Online Access: | http://eprints.usm.my/58615/1/Design%20Of%20FPGA-Based%20Encryption%20Chipusing%20Blowfish%20Algorithm_Khor%20Lay%20Hoong.pdf http://eprints.usm.my/58615/ |
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| Summary: | Nowadays, the world has changed so rapidly that everything has become digitized and computerized. Unfortunately, digital information is very easy to be duplicated, modified,
transmitted or used by unauthorized users. This results a serious problem and in view of this, some sort of security mechanism has to be produced to protect it. This is where the
study of cryptography comes in. Cryptography has been introduced to protect the information. However, until now, the cryptography hardware is still not commonly used especially in FPGA. In this project, the Blowfish encryption algorithm is chosen because it is among the safest algorithm used nowadays. The aim of this project is to design a Blowfish encryption chip in FPGA. For this project, the design entry used is
Altera’s Quartus II Version 5.0 and the targeted hardware is Altera’s Flex10K FPGA device. By using FPGA device, data can be encrypted or decrypted in real time and this would be a great tool for security purpose, such as ATM machine. The first stage of this project is the study of Blowfish algorithm and translates the method into VHDL code because VHDL has been commonly used as a design entry language for FPGA in digital
design. Producing the VHDL code is the most difficult and time-consuming part throughout this project. In the second stage, the design is realized using the FPGA board. In this stage, timing is the most critical factor that must be taken care of. If the timing is incorrect, the output may be wrong. Comparison will be done on the software result and hardware result to ensure that the encryption chip is designed correctly and function well. |
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