Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL
This report included code writing, schematic, layout and simulation result for front end and backend process. This design is actually done for digital signal processing and still need more effort in research since this project is still new in our university. Front end process consists of behav...
Saved in:
Main Author: | |
---|---|
Format: | Monograph |
Language: | English |
Published: |
Universiti Sains Malaysia
2006
|
Subjects: | |
Online Access: | http://eprints.usm.my/58610/1/Design%20Of%208%20Bits%20Parallel%20To-Serial%20Converter%20For%20Baseband%20Using%20VHDL_Ruhaifi%20Abdullah%20Zawawi.pdf http://eprints.usm.my/58610/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
id |
my.usm.eprints.58610 |
---|---|
record_format |
eprints |
spelling |
my.usm.eprints.58610 http://eprints.usm.my/58610/ Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL Abdullah Zawawi, Ruhaifi T Technology TK Electrical Engineering. Electronics. Nuclear Engineering This report included code writing, schematic, layout and simulation result for front end and backend process. This design is actually done for digital signal processing and still need more effort in research since this project is still new in our university. Front end process consists of behavioral description, RTL description and gate level description. Synthesis is done throughout this process to specify the maximum frequency for clock signal. This design has achieved frequency of 204MHz at typical process with 162238.88um2 in total area and only 0.0294mW in power consumption. Our target is to get high speed system to produce high data rate. We also want to reduce the power consumption especially the dynamic and static power. For front end, the design had been carried out for behavioral description, synthesis and verilog in for gate level simulation. Then, the gate level netlist will be imported for back end process included its timing constrain. A simple floorplan is generated, blocks or cells are placed, power routing is done and all analysis for timing, violation ,clock tree and fixing all problems in our layout . Our target is to get GDSII file with no violation in setup and hold time, also no signal integrity problems. For back end analysis, there are no violation since the slack minimum slack value is 6.553ns for rising edge signal and 7.739ns for falling edge signal. The last process is very important because the parasitic resistor and capacitance have been considered so that the timing and power analysis will be more accurate. In addition, clock tree synthesis is carried out to arrange all standard cells at certain place in the core so that the clock signal will arrive at same time for all cells. Universiti Sains Malaysia 2006-05-01 Monograph NonPeerReviewed application/pdf en http://eprints.usm.my/58610/1/Design%20Of%208%20Bits%20Parallel%20To-Serial%20Converter%20For%20Baseband%20Using%20VHDL_Ruhaifi%20Abdullah%20Zawawi.pdf Abdullah Zawawi, Ruhaifi (2006) Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL. Project Report. Universiti Sains Malaysia, Pusat Pengajian Kejuruteraan Elektrik dan Elektronik. (Submitted) |
institution |
Universiti Sains Malaysia |
building |
Hamzah Sendut Library |
collection |
Institutional Repository |
continent |
Asia |
country |
Malaysia |
content_provider |
Universiti Sains Malaysia |
content_source |
USM Institutional Repository |
url_provider |
http://eprints.usm.my/ |
language |
English |
topic |
T Technology TK Electrical Engineering. Electronics. Nuclear Engineering |
spellingShingle |
T Technology TK Electrical Engineering. Electronics. Nuclear Engineering Abdullah Zawawi, Ruhaifi Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL |
description |
This report included code writing, schematic, layout and simulation result for
front end and backend process. This design is actually done for digital signal processing
and still need more effort in research since this project is still new in our university. Front
end process consists of behavioral description, RTL description and gate level
description. Synthesis is done throughout this process to specify the maximum frequency
for clock signal. This design has achieved frequency of 204MHz at typical process with
162238.88um2
in total area and only 0.0294mW in power consumption. Our target is to
get high speed system to produce high data rate. We also want to reduce the power
consumption especially the dynamic and static power. For front end, the design had been
carried out for behavioral description, synthesis and verilog in for gate level simulation.
Then, the gate level netlist will be imported for back end process included its timing
constrain. A simple floorplan is generated, blocks or cells are placed, power routing is
done and all analysis for timing, violation ,clock tree and fixing all problems in our
layout . Our target is to get GDSII file with no violation in setup and hold time, also no
signal integrity problems. For back end analysis, there are no violation since the slack
minimum slack value is 6.553ns for rising edge signal and 7.739ns for falling edge
signal. The last process is very important because the parasitic resistor and capacitance
have been considered so that the timing and power analysis will be more accurate. In
addition, clock tree synthesis is carried out to arrange all standard cells at certain place in
the core so that the clock signal will arrive at same time for all cells. |
format |
Monograph |
author |
Abdullah Zawawi, Ruhaifi |
author_facet |
Abdullah Zawawi, Ruhaifi |
author_sort |
Abdullah Zawawi, Ruhaifi |
title |
Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL |
title_short |
Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL |
title_full |
Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL |
title_fullStr |
Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL |
title_full_unstemmed |
Design Of 8 Bits Parallel To-Serial Converter For Baseband Using VHDL |
title_sort |
design of 8 bits parallel to-serial converter for baseband using vhdl |
publisher |
Universiti Sains Malaysia |
publishDate |
2006 |
url |
http://eprints.usm.my/58610/1/Design%20Of%208%20Bits%20Parallel%20To-Serial%20Converter%20For%20Baseband%20Using%20VHDL_Ruhaifi%20Abdullah%20Zawawi.pdf http://eprints.usm.my/58610/ |
_version_ |
1768007906906603520 |
score |
13.160551 |