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Clock Gating Technique For Power Reduction In Digital Design

Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not g...

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Main Author: Khor, Peng Lim
Format: Thesis
Language:English
Published: 2012
Subjects:
TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Online Access:http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf
http://eprints.usm.my/44825/
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id my.usm.eprints.44825
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spelling my.usm.eprints.44825 http://eprints.usm.my/44825/ Clock Gating Technique For Power Reduction In Digital Design Khor, Peng Lim TK1-9971 Electrical engineering. Electronics. Nuclear engineering Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not give the same power saving efficiency when the operating frequency increases. Power reduction effectiveness decreases follows downward of the design flow. For an IC design house without fabrication factory, levels of power optimization in the design flow are very limited. 2012-12 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf Khor, Peng Lim (2012) Clock Gating Technique For Power Reduction In Digital Design. Masters thesis, Universiti Sains Malaysia.
institution Universiti Sains Malaysia
building Hamzah Sendut Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Sains Malaysia
content_source USM Institutional Repository
url_provider http://eprints.usm.my/
language English
topic TK1-9971 Electrical engineering. Electronics. Nuclear engineering
spellingShingle TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Khor, Peng Lim
Clock Gating Technique For Power Reduction In Digital Design
description Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not give the same power saving efficiency when the operating frequency increases. Power reduction effectiveness decreases follows downward of the design flow. For an IC design house without fabrication factory, levels of power optimization in the design flow are very limited.
format Thesis
author Khor, Peng Lim
author_facet Khor, Peng Lim
author_sort Khor, Peng Lim
title Clock Gating Technique For Power Reduction In Digital Design
title_short Clock Gating Technique For Power Reduction In Digital Design
title_full Clock Gating Technique For Power Reduction In Digital Design
title_fullStr Clock Gating Technique For Power Reduction In Digital Design
title_full_unstemmed Clock Gating Technique For Power Reduction In Digital Design
title_sort clock gating technique for power reduction in digital design
publishDate 2012
url http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf
http://eprints.usm.my/44825/
_version_ 1643711115587223552
score 13.211869

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