Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
In recent years, finger vein recognition has emerged as a promising biometric technology due to the fact that each person in this world has unique finger vein pattern. Over the past few years, various finger vein recognition algorithms and techniques have been proposed by researchers and scholars. T...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2016
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| Subjects: | |
| Online Access: | http://eprints.usm.my/41321/1/YEW_TZE_EE_24_Pages.pdf http://eprints.usm.my/41321/ |
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| Summary: | In recent years, finger vein recognition has emerged as a promising biometric technology due to the fact that each person in this world has unique finger vein pattern. Over the past few years, various finger vein recognition algorithms and techniques have been proposed by researchers and scholars. The challenge of finger vein recognition in becoming mainstream biometric technology is the processing time of recognition. As almost all finger vein recognition algorithms were implemented using software such as MATLAB which is based on general-purpose processor, the processing speed become the bottleneck of the development of finger vein recognition. In order to increase the processing, this thesis introduces an architecture for finger vein recognition based on K-Nearest Centroid Neighbors (KNCN) classifier implemented on Field Programmable Gate Array (FPGA). KNCN is a type of classification technique in image processing which involves calculation of centroid and sorting of K-nearest centroid neighbors. FPGA enables parallel computation in contrasts to serial computation in general processor. The proposed architecture is written in Verilog Hardware Description Language (HDL) and programmed into Altera Development and Educational Board, DE2-115 through Quartus II 15.0. An image database which consists of 80 finger vein classes has been used to evaluate the accuracy and processing time of the proposed architecture. Experimental results showed that the processing time of the hardware architecture for KNCN classifier implemented on FPGA for one testing image is 4.98 ms, which is 9 times faster than software implementation of KNCN classifier. The accuracy of the hardware architecture is 77% which is slightly lower than the accuracy in MATLAB. In conclusion, the finger vein identification hardware architecture based on KNCN classifier is successfully implemented on an FPGA board with faster processing time as compared with software-based implementation of KNCN classifier in MATLAB. |
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