Low Power Design Of 8b/10b Encoder And 10b/8b Decoder Using Clock Gating Technique

• Main Author: Ong, Ji Xian
• Format: Thesis
• Language: English
• Published: 2017
• Subjects: TK1-9971 Electrical engineering. Electronics. Nuclear engineering
• Online Access: http://eprints.usm.my/39575/1/ONG_JI_XIAN_24_Pages.pdf; http://eprints.usm.my/39575/

8B/10B Encoder and 10B/8B Decoder can be found in most of the high transmission speed electronic application such as Serial ATA (SATA), Universal Serial Bus (USB) 3.0 and optical fiber applications. This is due to the DC balance, not more than five consecutive bits which leads to reliable clock recovery and easiness of error detection of the encoded data. Due to the market demand of portable devices, the low power design become one of the critical design concern of electronic circuit. Since 8B/10B Encoder will be using in the high speed data transferring components, low power design of the encoder will be needed by the market. In this project two implementation of 8B/10B Encoder and 10B/8B Decoder are designed and implement with clock gating circuit. The logical implementation method is designed from finding the boolean logic of every output, while behavioral implementation method is designed by only behavioral of the encoder/decoder. All the circuits were designed with Verilog Hardware Description Language (HDL) and simulated with ModelSim. The clock gating circuit is simple, easy to be implemented to the circuit and effectively reduce the clock activity, eventually reduced the dynamic power of the circuit. The power analysis is done under 20 MHz and 200 MHz clock frequencies with the help of Xilinx Power Analysis Tool. At 20 MHz, 38.24 % of the hierarchy power has been reduced for clock gated 8B/10B Encoder and 8.33 % reduction for clock gated 10B/8B Decoder. At 200 MHz, 45.28 % of the hierarchy power has been reduced for clock gated 8B/10B Encoder and 8.47 % reduction for clock gated 10B/8B Decoder.