Correlation Methodology between Silicon and HSPICE Simulation of AC IO Buffer

• Main Author: Balamahesn, Poongan
• Format: Thesis
• Language: English
• Published: Universiti Sains Malaysia 2017
• Subjects: QC170-197 Atomic physics Constitution and properties of matter Including molecular physics, relativity, quantum theory, and solid state physics; TK Electrical Engineering. Electronics. Nuclear Engineering
• Online Access: http://eprints.usm.my/35993/1/BALAMAHESN_POONGAN_CORRELATION_METHODOLOGY_BETWEEN_SILICON_AND_HSPICE_SIMULATION_OF_AC_IO_BUFFER_2017_MSc_E%26E_BSB_24.pdf; http://eprints.usm.my/35993/

Dalam era teknologi terkini, sistem yang mempunyai berkeupayaan tinggi dan reka bentuk yang rumit memberi kesulitan kepada pereka bentuk. Keupayaan untuk mensimulasi reka bentuk komplek sebelum diberikan kepada pelanggan telah bertukar menjadi asas kepada pencapaian projek. Berdasarkan kepada pandangan pengilang, pemberian model HSPICE sangat berisiko kerana harta intelek (IP) penimbal IO yang sulit mungkin tersebar kepada orang luar. Pihak industri kebiasaannya mengedarkan model IBIS yang mengandungi teknik tingkah laku bagi memaparkan penimbal IO daripada model HSPICE tersebut. Maka, korelasi antara model HSPICE dan silikon menjadi penting bagi memberi lebih keyakinan dan meningkatkan kebolehpercayaan dan ketepatan model IBIS yang akan diedarkan kepada pelanggan. Dengan itu, kajian ini dijalankan untuk mencadangkan model korelasi bagi penimbal AC IO di antara simulasi HSPICE dan silikon secara cekap dan sifar kesilapan. Di dalam kerja penyelidikan ini, penimbal AC IO diuji berdasarkan masa menaik dan masa menurun bagi isyarat keluarannya. Dengan melaksanakan model korelasi ini, kebolehpercayaan model IBIS dari segi pemasaannya dapat memastikan keserasian dengan silikon secara berkesan. Bagi penyelidikan ini, hasilnya, proses sudut pantas dan tipikal memenuhi sasaran korelasi yang ditetapkan pada ± 20%, manakala proses sudut perlahan telah gagal memenuhi sasaran. In this technology era, the high-performance systems that include complexity on the design make noteworthy difficulties to board designers. The capacity to simulate the complex design before laying out the board has turned into a basic consideration for the accomplishment of a project. Based on manufacturer’s viewpoint, releasing a HSPICE model is a high risk, since the confidentiality of IO Buffer intellectual property (IP) might be exposed to outsiders. Industries usually distribute the IBIS model in which behavioral technique for displaying IO buffers is obtained from the HSPICE model. Therefore, correlation between the HSPICE model and silicon become significant to increase the reliability and accuracy of IBIS model which would be released to the customer. Hence, this research was carried forward to initiate correlation model for correlation of the HSPICE and silicon of AC IO buffer, in an efficient and error free manner. AC IO buffer is one of the important features needed to ensure reliability of IBIS model before handing over to the customer. In this work, AC IO buffer is tested on the rising time and falling time of output signal from the IO buffer. By implementing this correlation model, the timing of the IBIS model could ensure compatibility with silicon effectively. As a result, the fast and typical process corners meet the correlation target which was set within ±20%, but slow process corner was not meeting the target.