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Implementation of multi-class shared buffer with finite memory size

High packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed...

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Main Authors: A.A.A., Rahman,, K., Seman,, K., Saadan,, A., Azman,
Format: Conference Paper
Language:en_US
Published: 2015
Subjects:
architecture design
finite memory size
FPGA
multi-class
Shared buffer
Online Access:http://ddms.usim.edu.my/handle/123456789/9208
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spelling my.usim-92082015-08-25T07:02:46Z Implementation of multi-class shared buffer with finite memory size A.A.A., Rahman, K., Seman, K., Saadan, A., Azman, architecture design finite memory size FPGA multi-class Shared buffer High packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16x16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch. © 2011 IEEE. 2015-08-25T07:02:46Z 2015-08-25T07:02:46Z 2011 Conference Paper 9781-4577-0388-1 http://ddms.usim.edu.my/handle/123456789/9208 en_US
institution Universiti Sains Islam Malaysia
building USIM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universit Sains Islam i Malaysia
content_source USIM Institutional Repository
url_provider http://ddms.usim.edu.my/
language en_US
topic architecture design
finite memory size
FPGA
multi-class
Shared buffer
spellingShingle architecture design
finite memory size
FPGA
multi-class
Shared buffer
A.A.A., Rahman,
K., Seman,
K., Saadan,
A., Azman,
Implementation of multi-class shared buffer with finite memory size
description High packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16x16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch. © 2011 IEEE.
format Conference Paper
author A.A.A., Rahman,
K., Seman,
K., Saadan,
A., Azman,
author_facet A.A.A., Rahman,
K., Seman,
K., Saadan,
A., Azman,
author_sort A.A.A., Rahman,
title Implementation of multi-class shared buffer with finite memory size
title_short Implementation of multi-class shared buffer with finite memory size
title_full Implementation of multi-class shared buffer with finite memory size
title_fullStr Implementation of multi-class shared buffer with finite memory size
title_full_unstemmed Implementation of multi-class shared buffer with finite memory size
title_sort implementation of multi-class shared buffer with finite memory size
publishDate 2015
url http://ddms.usim.edu.my/handle/123456789/9208
_version_ 1645152562909806592
score 13.211869

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