Cell drop threshold architecture for multi-class shared buffer with finite memory size

Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this pa...

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Main Authors: A.A., Abdul Rahman,, K., Seman,, K., Saadan,, A.K., Samingan,, A., Azman,
Format: Conference Paper
Language:en_US
Published: 2015
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Online Access:http://ddms.usim.edu.my/handle/123456789/9139
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spelling my.usim-91392015-08-24T03:34:45Z Cell drop threshold architecture for multi-class shared buffer with finite memory size A.A., Abdul Rahman, K., Seman, K., Saadan, A.K., Samingan, A., Azman, architecture design cell drop threshold multi-class Shared buffer Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this paper, we analyse the performance of shared buffer with different threshold settings. The multi-class shared buffer architecture is developed for 16x16 ports switch, which is targeted for Xilinx FPGA implementation. The performance of the multi-class shared buffer switch is analysed in term of the achievable throughput as well as the drop probability. Based on the simulation with different threshold settings, it is observed that the optimum selection of cell drop threshold depends on the size of the shared buffer that triggers the RAM threshold. © 2011 IEEE. 2015-08-24T03:34:45Z 2015-08-24T03:34:45Z 2011 Conference Paper 9781-4577-2058-1 http://ddms.usim.edu.my/handle/123456789/9139 en_US
institution Universiti Sains Islam Malaysia
building USIM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universit Sains Islam i Malaysia
content_source USIM Institutional Repository
url_provider http://ddms.usim.edu.my/
language en_US
topic architecture design
cell drop threshold
multi-class
Shared buffer
spellingShingle architecture design
cell drop threshold
multi-class
Shared buffer
A.A., Abdul Rahman,
K., Seman,
K., Saadan,
A.K., Samingan,
A., Azman,
Cell drop threshold architecture for multi-class shared buffer with finite memory size
description Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this paper, we analyse the performance of shared buffer with different threshold settings. The multi-class shared buffer architecture is developed for 16x16 ports switch, which is targeted for Xilinx FPGA implementation. The performance of the multi-class shared buffer switch is analysed in term of the achievable throughput as well as the drop probability. Based on the simulation with different threshold settings, it is observed that the optimum selection of cell drop threshold depends on the size of the shared buffer that triggers the RAM threshold. © 2011 IEEE.
format Conference Paper
author A.A., Abdul Rahman,
K., Seman,
K., Saadan,
A.K., Samingan,
A., Azman,
author_facet A.A., Abdul Rahman,
K., Seman,
K., Saadan,
A.K., Samingan,
A., Azman,
author_sort A.A., Abdul Rahman,
title Cell drop threshold architecture for multi-class shared buffer with finite memory size
title_short Cell drop threshold architecture for multi-class shared buffer with finite memory size
title_full Cell drop threshold architecture for multi-class shared buffer with finite memory size
title_fullStr Cell drop threshold architecture for multi-class shared buffer with finite memory size
title_full_unstemmed Cell drop threshold architecture for multi-class shared buffer with finite memory size
title_sort cell drop threshold architecture for multi-class shared buffer with finite memory size
publishDate 2015
url http://ddms.usim.edu.my/handle/123456789/9139
_version_ 1645152548074553344
score 13.211869