Low power multicarrier- code division multiple access receiver on field programmable gate array

This paper presents a low power multi-carrier code division multiple access (MC-CDMA) receiver on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor networks, portable computation and many more require a low power design. Time-division multiple acc...

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Main Authors: Mohd Hassan, Siti Lailatul, Sulaiman, Nasri, Saparon, Azilah, Mohd Yussoff, Yusnani, Jaafar, Haslina
Format: Article
Language:English
Published: World Academy of Research in Science and Engineering 2019
Online Access:http://psasir.upm.edu.my/id/eprint/81250/1/POWER.pdf
http://psasir.upm.edu.my/id/eprint/81250/
http://www.warse.org/IJATCSE/years/archivesDetiles/?heading=Volume%208%20No.%201.6%20(2019)%20S%20I
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spelling my.upm.eprints.812502021-06-16T00:05:32Z http://psasir.upm.edu.my/id/eprint/81250/ Low power multicarrier- code division multiple access receiver on field programmable gate array Mohd Hassan, Siti Lailatul Sulaiman, Nasri Saparon, Azilah Mohd Yussoff, Yusnani Jaafar, Haslina This paper presents a low power multi-carrier code division multiple access (MC-CDMA) receiver on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor networks, portable computation and many more require a low power design. Time-division multiple access (TDMA) is used in most wireless receivers are not very efficient since they adopt scheduling technique. The first objective of this paper is to design and verify a low power MC-CDMA receiver and the second objective is to implement the MC-CDMA receiver on FPGA. MC-CDMA act as a processor with the ability to process transmit or receive data simultaneously over a single communication channel. The MC-CDMA design in this paper consists of pipelined FFT and combiner. The primary purpose of pipelined FFT plus combiner module in this research is to execute the instruction on communication (data send and receive) and self-organization. Besides these two modules, there is a memory for temporarily storing the data and an internal clock, among other things. To accomplish these, the designs have been carried out using Verilog coding in Modelsim software, and the design verifications are done through Matlab. The design implementation is via Quartus and on DE2-115 Altera FPGA board. The functionality analyses have been carried out on simulation, and the hardware implementation of the MC-CDMA receiver is tested. Both simulation and hardware execution are successful where the receiver received and displayed the output accordingly. MC-CDMA achieves 39.13mW total power consumption. World Academy of Research in Science and Engineering 2019 Article PeerReviewed text en http://psasir.upm.edu.my/id/eprint/81250/1/POWER.pdf Mohd Hassan, Siti Lailatul and Sulaiman, Nasri and Saparon, Azilah and Mohd Yussoff, Yusnani and Jaafar, Haslina (2019) Low power multicarrier- code division multiple access receiver on field programmable gate array. International Journal of Advanced Trends in Computer Science and Engineering, 8 (1 spec. 6). pp. 318-323. ISSN 2278-3091 http://www.warse.org/IJATCSE/years/archivesDetiles/?heading=Volume%208%20No.%201.6%20(2019)%20S%20I 10.30534/ijatcse/2019/4781.62019
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description This paper presents a low power multi-carrier code division multiple access (MC-CDMA) receiver on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor networks, portable computation and many more require a low power design. Time-division multiple access (TDMA) is used in most wireless receivers are not very efficient since they adopt scheduling technique. The first objective of this paper is to design and verify a low power MC-CDMA receiver and the second objective is to implement the MC-CDMA receiver on FPGA. MC-CDMA act as a processor with the ability to process transmit or receive data simultaneously over a single communication channel. The MC-CDMA design in this paper consists of pipelined FFT and combiner. The primary purpose of pipelined FFT plus combiner module in this research is to execute the instruction on communication (data send and receive) and self-organization. Besides these two modules, there is a memory for temporarily storing the data and an internal clock, among other things. To accomplish these, the designs have been carried out using Verilog coding in Modelsim software, and the design verifications are done through Matlab. The design implementation is via Quartus and on DE2-115 Altera FPGA board. The functionality analyses have been carried out on simulation, and the hardware implementation of the MC-CDMA receiver is tested. Both simulation and hardware execution are successful where the receiver received and displayed the output accordingly. MC-CDMA achieves 39.13mW total power consumption.
format Article
author Mohd Hassan, Siti Lailatul
Sulaiman, Nasri
Saparon, Azilah
Mohd Yussoff, Yusnani
Jaafar, Haslina
spellingShingle Mohd Hassan, Siti Lailatul
Sulaiman, Nasri
Saparon, Azilah
Mohd Yussoff, Yusnani
Jaafar, Haslina
Low power multicarrier- code division multiple access receiver on field programmable gate array
author_facet Mohd Hassan, Siti Lailatul
Sulaiman, Nasri
Saparon, Azilah
Mohd Yussoff, Yusnani
Jaafar, Haslina
author_sort Mohd Hassan, Siti Lailatul
title Low power multicarrier- code division multiple access receiver on field programmable gate array
title_short Low power multicarrier- code division multiple access receiver on field programmable gate array
title_full Low power multicarrier- code division multiple access receiver on field programmable gate array
title_fullStr Low power multicarrier- code division multiple access receiver on field programmable gate array
title_full_unstemmed Low power multicarrier- code division multiple access receiver on field programmable gate array
title_sort low power multicarrier- code division multiple access receiver on field programmable gate array
publisher World Academy of Research in Science and Engineering
publishDate 2019
url http://psasir.upm.edu.my/id/eprint/81250/1/POWER.pdf
http://psasir.upm.edu.my/id/eprint/81250/
http://www.warse.org/IJATCSE/years/archivesDetiles/?heading=Volume%208%20No.%201.6%20(2019)%20S%20I
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score 13.160551