Optimising the space utilisation in real-time flash translation layer mapping scheme

• Main Authors: Ab. Karim, Mohd Bazli, Rahiman, Amir Rizaan, Latip, Rohaya, Ibrahim, Hamidah
• Format: Article
• Language: English
• Published: Science Publishing Corporation 2018
• Online Access: http://psasir.upm.edu.my/id/eprint/75153/1/Optimising%20the%20space%20utilisation%20in%20real-time%20flash%20translation%20layer%20mapping%20scheme.pdf; http://psasir.upm.edu.my/id/eprint/75153/

Solid-State Disk (SSD) is a semiconductor storage device and it has become a preferred choice for many storage sub-systems solutions to replace the classical hard drives due to its high performance and durability. Moreover, NAND flash memory has become cheaper in costs. However, this flash memory type has its own limitations due to its erase-before-write operations nature. This limitation will cause the memory to wear faster and consuming higher cost when initiating the cleaning process. To overcome the limitation, an address mapping in NAND flash memory namely Flash Translation Layer (FTL) plays important role in handling I/O operations. Several studies on the FTL have been carried out to manage the IO operations in NAND flash device efficiently. This paper proposed an optimized address-mapping scheme called Optimized Real-Time Flash Translation Layer (ORFTL). In order to increase the NAND flash space utilization, the proposed scheme reduces idle buffer blocks and reassigns the blocks as new Logical Block Addressing (LBA) in order to optimize blocks in flash memory for more space utilization. In addition, the scheme introduces a pool of buffer blocks with the same bandwidth throughput size of IO interface that connects the SSD to the host system in order to guarantee available free spaces to serve write operations. By optimizing both types of blocks, the proposed scheme has shown significant increases in the NAND flash memory space utilization as compared to the existing FTL schemes.