Numerical study of side gate junction-less transistor in on state
Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in...
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Main Authors: | , , , , , , , , |
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Format: | Conference or Workshop Item |
Language: | English |
Published: |
IEEE
2013
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Online Access: | http://psasir.upm.edu.my/id/eprint/68136/1/Numerical%20study%20of%20side%20gate%20junction-less%20transistor%20in%20on%20state.pdf http://psasir.upm.edu.my/id/eprint/68136/ |
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