Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA

• Main Authors: Al-Hussaini, Khalid Taher Mohammed, Mohd Ali, Borhanuddin, Varahram, Pooria, Hashim, Shaiful Jahari, Farrell, Ronan
• Format: Article
• Language: English
• Published: Inderscience 2017
• Online Access: http://psasir.upm.edu.my/id/eprint/62006/1/Hardware%20co-simulation%20for%20a%20low%20complexity%20PAPR%20reduction%20scheme%20on%20an%20FPGA.pdf; http://psasir.upm.edu.my/id/eprint/62006/; https://www.inderscienceonline.com/doi/abs/10.1504/IJWMC.2017.083053

This paper presents a novel low-complexity technique for reducing the Peak-to-Average Power Ratio PAPR in Orthogonal Frequency Division Multiplexing OFDM systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on a Field Programmabl...