Fault tolerance of L1 data cache memory induced by intrinsic parameters fluctuation in sub 10nm UTB-SOI MOSFETs
Currently, the development of models at higher level of abstractions (system-level) to be able to incorporate effects at lower levels of abstractions (process /transistor) is in demand. This thesis addresses issues to enabling computer system simulation model in the presence of cell failures in L1 d...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2013
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56181/1/FK%202013%20116RR.pdf http://psasir.upm.edu.my/id/eprint/56181/ |
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