Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter

• Main Authors: Mohamad, Ahmad Syukri, Mariun, Norman
• Format: Conference or Workshop Item
• Language: English
• Published: IEEE 2016
• Online Access: http://psasir.upm.edu.my/id/eprint/56004/1/Simulation%20of%20a%2041-level%20inverter%20built%20by%20cascading%20two%20symmetric%20cascaded%20multilevel%20inverter.pdf; http://psasir.upm.edu.my/id/eprint/56004/

The main disadvantage for cascaded multilevel inverter is the high number of switching device it needs in an installation. To reduce total harmonics distortion (THD) of the output waveform, the number of output voltage level has to be increased, hence the higher number of switching devices. This consequently increases the installation cost, inverter size and voltage losses at the load terminals. In this paper a new cascaded multilevel inverter concept is proposed with a small number of switching devices and dc sources needed. The 41-level inverter consist of several high voltage and low voltage dc sources. The switching strategy of the inverter is the low voltage dc sources are switched in several times in a half cycle of the output. The 41-level cascaded multilevel inverter operation is then demonstrated by the Matlab simulation.