Design high frequency surgical robot controller: design FPGA-based controller for surgical robot manipulator simscape modeling

• Main Authors: Taghizadegan, Ali, Piltan, Farzin, Sulaiman, Nasri B.
• Format: Article
• Language: English
• Published: Science and Engineering Research Support Society 2016
• Online Access: http://psasir.upm.edu.my/id/eprint/55450/1/Design%20high%20frequency%20surgical%20robot%20controller.pdf; http://psasir.upm.edu.my/id/eprint/55450/; http://www.sersc.org/journals/IJHIT/

Recent developments of robotics allocated many of industrial and medical activities. So that most of industries turned to use surgical robots in their production line or in their surgery. Being precise, spent less time-consuming, present uniform quality with less cost and reducing waste and energy are some advantages of using robots in industry. This paper has two important objectives: a) study on modeling and controlling of 4 degrees of freedom (DOF) based on Simscape software and b) design FPGA-based controller for this type of surgical robot manipulator. Simscape provides an environment for modeling and simulating physical systems. Simscape modeling can be designed to control and test system-level performance. Conventional PID controller is a stable linear type model-free controller that reduces the delay time in highly nonlinear system. In this research, linear controller need real time mobility operation, and one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA). FPGA can be used to design a controller in a single chip Integrated Circuit (IC). To design PID type FPGA-based controller two types algorithm are needed: derivative algorithm and integral algorithm. In HDL based derivative algorithm the minimum input arrival time before clock is 16.466 ns and the maximum frequency is 60.73 MHz, but in the best design action, the maximum frequency to design this single chip algorithm should be 63.629 MHz. In HDL integral algorithm the minimum input arrival time before clock is 15.599 ns and the maximum frequency is 64.1 MHz, but in the best design action, the maximum frequency to design this single chip algorithm should be 178.190 MHz.