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The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

Purpose – This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach – The code uses a generator matrix designed for four-state space time trellis code (STTC) that use...

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Main Authors: Abu, Mohd Azlan, Harun, Harlisya, Harmin, Mohammad Yazdi, Abdul Wahab, Noor Izzri, Abdul Kadir, Muhd Khairulzaman
Format: Article
Language:English
Published: Emerald Group Publishing 2016
Online Access:http://psasir.upm.edu.my/id/eprint/52962/1/The%20design%20of%20viterbi%20decoder%20for%20low%20power%20consumption%20space%20time%20trellis%20code%20without%20adder%20architecture%20using%20RTL%20model.pdf
http://psasir.upm.edu.my/id/eprint/52962/
http://www.multi-science.co.uk/wje.htm
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spelling my.upm.eprints.529622017-11-27T06:12:54Z http://psasir.upm.edu.my/id/eprint/52962/ The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model Abu, Mohd Azlan Harun, Harlisya Harmin, Mohammad Yazdi Abdul Wahab, Noor Izzri Abdul Kadir, Muhd Khairulzaman Purpose – This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach – The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm. Findings – The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps. Originality/value – It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review. Emerald Group Publishing 2016 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/52962/1/The%20design%20of%20viterbi%20decoder%20for%20low%20power%20consumption%20space%20time%20trellis%20code%20without%20adder%20architecture%20using%20RTL%20model.pdf Abu, Mohd Azlan and Harun, Harlisya and Harmin, Mohammad Yazdi and Abdul Wahab, Noor Izzri and Abdul Kadir, Muhd Khairulzaman (2016) The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model. World Journal of Engineering, 13 (6). pp. 540-546. ISSN 1708-5284; ESSN: 1708-5284 http://www.multi-science.co.uk/wje.htm 10.1108/WJE-09-2016-0088
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description Purpose – This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach – The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm. Findings – The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps. Originality/value – It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.
format Article
author Abu, Mohd Azlan
Harun, Harlisya
Harmin, Mohammad Yazdi
Abdul Wahab, Noor Izzri
Abdul Kadir, Muhd Khairulzaman
spellingShingle Abu, Mohd Azlan
Harun, Harlisya
Harmin, Mohammad Yazdi
Abdul Wahab, Noor Izzri
Abdul Kadir, Muhd Khairulzaman
The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
author_facet Abu, Mohd Azlan
Harun, Harlisya
Harmin, Mohammad Yazdi
Abdul Wahab, Noor Izzri
Abdul Kadir, Muhd Khairulzaman
author_sort Abu, Mohd Azlan
title The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
title_short The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
title_full The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
title_fullStr The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
title_full_unstemmed The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
title_sort design of viterbi decoder for low power consumption space time trellis code without adder architecture using rtl model
publisher Emerald Group Publishing
publishDate 2016
url http://psasir.upm.edu.my/id/eprint/52962/1/The%20design%20of%20viterbi%20decoder%20for%20low%20power%20consumption%20space%20time%20trellis%20code%20without%20adder%20architecture%20using%20RTL%20model.pdf
http://psasir.upm.edu.my/id/eprint/52962/
http://www.multi-science.co.uk/wje.htm
_version_ 1643835304314929152
score 13.212156

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