Design of FPGA-based Sliding Mode Controller for Robot Manipulator.

One of the most active research areas in the field of robotics is robot manipulators control, because these systems are multi-input multi-output (MIMO), nonlinear, and uncertainty. At present, robot manipulators is used in unknown and unstructured situation and caused to provide complicated syste...

Full description

Saved in:
Bibliographic Details
Main Authors: Sulaiman, Nasri, Marhaban, Mohammad Hamiruce, Piltan, Farzin, Nowzary, Adel, Tohidian, Mostafa
Format: Article
Language:English
Published: 2011
Online Access:http://psasir.upm.edu.my/id/eprint/23393/
http://www.cscjournals.org/csc/manuscript/Journals/IJRA/volume2/Issue3/IJRA-40.pdf
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:One of the most active research areas in the field of robotics is robot manipulators control, because these systems are multi-input multi-output (MIMO), nonlinear, and uncertainty. At present, robot manipulators is used in unknown and unstructured situation and caused to provide complicated systems, consequently strong mathematical tools are used in new control methodologies to design nonlinear robust controller with satisfactory performance (e.g., minimum error, good trajectory, disturbance rejection). Robotic systems controlling is vital due to the wide range of application. Obviously stability and robustness are the most minimum requirements in control systems; even though the proof of stability and robustness is more important especially in the case of nonlinear systems. One of the best nonlinear robust controllers which can be used in uncertainty nonlinear systems is sliding mode controller (SMC). Chattering phenomenon is the most important challenge in this controller. Most of nonlinear controllers need real time mobility operation; one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA). FPGA can be used to design a controller in a single chip Integrated Circuit (IC). In this research the SMC is designed using VHDL language for implementation on FPGA device (XA3S1600E-Spartan-3E), with minimum chattering and high processing speed (63.29 MHz).