Design of 8-Bit CMOS Digital to Analog Converter

• Main Author: Tan, Gim Heng
• Format: Thesis
• Language: English; English
• Published: 2001
• Online Access: http://psasir.upm.edu.my/id/eprint/11023/1/FK_2001_40_A.pdf; http://psasir.upm.edu.my/id/eprint/11023/

Digital to analog converter (DAC) is the main link between the digital and analog signal in the world of signal processing. High-speed DAC has been used widely as the data converter in video, radar and communication application. This project presents a high-speed current switching CMOS digital analog converter (DAC) that achieves 8-bit resolution with good differential non-linearity (DNL). The use of current switching creates a potential for speed improvement because current can be switch in and out of a circuit faster than the voltage. This converter is based on current division by using segmentation technique. In this approach, low DNL and glitch energy can be achieved by segmenting the two or three most significant bits of the DAC with an array of equal current sources rather than a binary array of current sources. This proposed segmented DAC employs two internal DACs that have its own advantages. The first internal DAC is used for the upper 3-bits MSBs. It is implemented by using equal current sources 0.25mA, with the incoming 3-bits MSBs converted to 7 control lines by the thermometer decoder, which will enable the 7-switched current cells. Thermometer decoder ensures good differential linearity for the DAC. The remaining 5 LSB bits of the converter will be controlled by the second internal DAC that use the R2R network to binary weight the O.25mA current source. The circuit of the DAC is designed by dividing into modules. The modules include thermometer decoder, latch, 5-bit LSB inverted R-2R ladder, 3-bit MSB current source, two-way CMOS current switch and the current to voltage converter. This circuit is simulated by using Tanner Tools Pro software, where the SCNA20um CMOS process with level-2 transistor parameters is used. The simulation results of the designed DAC shows a conversion rate of 7.2Mhz, a lNL of ±1.36 LSB, a DNL of ±D.05 LSB and a glitch energy of 30p V s with the power supply of ± 5V. The reduced differential nonlinearity (DNL) is achieved by utilizing the proposed technique.