Enabling multithreading executions on the XILINX microkernel with a hardware scheduler

• Main Authors: Harmin Y.S., Jidin R., Moubark A.M., Zainol M.A.
• Other Authors: 24733821700
• Format: Conference paper
• Published: 2023
• Subjects: Field programmable gate arrays (FPGA); Hardware; Scheduling; Fair sharing; Hardware threads; Improving systems; Initial designs; Input/output; Instruction scheduling; Intellectual property cores; Multiple processors; Multithreading; Scheduling mechanisms; Scheduling tasks; Sharing schemes; Multitasking

Multithreading programming can improve performance of an application especially to reduce processor busy waiting. Typically, threads that have to wait for input/output responses can wait in a queue (sleep queue), allowing other threads to utilize processor, therefore improving system timeliness and throughput. As such an application can be partitioned into several threads that can be executed on either single or multiple processors. Sharing of processors among threads however requires scheduling to ensure fair sharing scheme or to meet a specific execution objective. The scheduling mechanism serves to allocate which threads get to run on a processor alternately according to the adopted sharing scheme. Processor can be relieved of executing the required scheduling task if it can be performed by a hardware entity such as Field Programmable Gate Array (FPGA). This paper describes initial design of hardware scheduler and modification of thread manager to support the migration (of thread scheduler into the hardware). The scheduler is designed as an Intellectual Property (IP) core that can be instantiated like any peripheral core. The work is intended to enable multithreading on XILINX microkernel with a hardware thread scheduler instead of Von Neumann stored instruction scheduling execution. �2008 IEEE.