FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection

• Main Authors: Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Ping L.C.
• Other Authors: 35974769600
• Format: Article
• Published: 2023
• Subjects: ADC with peak detector block; Counter with reset block; FPGA simulation; FPGA technology; Partial discharge detection; Real time processing; Underground cable; VHDL programming

Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns.