VHDL implementation for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe for the PD detection circuit system by using 3 GHz ADC and FPGA

• Main Authors: Emilliano, Chakrabarty C.K., Ghani A.B.A., Ramasamy A.K.
• Other Authors: 35974769600
• Format: Conference paper
• Published: 2023
• Subjects: 64 Bit BCD Counter with Reset Block; 64 Bit Latch Block; ADC with Peak Detector Block; FPGA Simulation; FPGA Technology; Partial Discharge Detection; Real Time Processing; Reset Automatic Block; Underground Cable; VHDL Programming; Cables; Computer hardware description languages; Detectors; Exhibitions; Field programmable gate arrays (FPGA); Partial discharges; Probes; Technology; Underground cables; FPGA technology; Partial discharge detection; Peak detectors; Realtime processing; Signal detection

This paper is purely a model to implement Partial Discharge (PD) detection in FPGA technology and then implement the VHDL modeled in FPGA technology for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe using 3GHz ADC (ADC083000RB-Reference Board) and impulse generator. Partial discharge (PD) is a well known phenomenon that causes insulation degradation in cross linked polyethylene (XLPE) power cable and ultimately it will cause insulation failure. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA-Xilinx Virtex 5 ML501 Board) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the field can have a bandwith of about 200 - 600 MHz. The output signals of the combination 4 blocks (peak detector block, 64 bit BCD counter with reset block, reset automatic block and 64 bit BCD counter) is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using Xilinx ISE simulator and implemented by ISE Xilinx Synthesized Technology and Xilinx ISE Implement Design. The distance resolution measurement of magnetic field is shown in this paper. � 2011 IEEE.