持有資料: Scaling down of the 32 nm to 22 nm gate length NMOS transistor

Scaling down of the 32 nm to 22 nm gate length NMOS transistor

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate in...

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Main Authors:	Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.
其他作者:	36570222300
格式:	Conference paper
出版:	2023
主題:	high-k/metal gate Scaling down ratio Silvaco Leakage currents Silicides Tungsten Design and simulation Design simulations Down-scaling Electrical characterization Fabrication tool Gate length Metal gate NMOS transistors Optimal values Scale down Scaling down TiO Tungsten silicide Titanium dioxide
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Scaling down of the 32 nm to 22 nm gate length NMOS transistor

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