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Scaling down of the 32 nm to 22 nm gate length NMOS transistor

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate in...

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Main Authors:	Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.
Other Authors:	36570222300
Format:	Conference paper
Published:	2023
Subjects:	high-k/metal gate Scaling down ratio Silvaco Leakage currents Silicides Tungsten Design and simulation Design simulations Down-scaling Electrical characterization Fabrication tool Gate length Metal gate NMOS transistors Optimal values Scale down Scaling down TiO Tungsten silicide Titanium dioxide
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id	my.uniten.dspace-29515
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spelling	my.uniten.dspace-295152024-09-09T11:18:49Z Scaling down of the 32 nm to 22 nm gate length NMOS transistor Afifah Maheran A.H. Menon P.S. Ahmad I. Elgomati H.A. Majlis B.Y. Salehuddin F. 36570222300 57201289731 12792216600 36536722700 6603071546 36239165300 high-k/metal gate Scaling down ratio Silvaco Leakage currents Silicides Tungsten Design and simulation Design simulations Down-scaling Electrical characterization Fabrication tool Gate length Metal gate NMOS transistors Optimal values Scale down Scaling down Silvaco TiO Tungsten silicide Titanium dioxide In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. � 2012 IEEE. Final 2023-12-28T06:30:18Z 2023-12-28T06:30:18Z 2012 Conference paper 10.1109/SMElec.2012.6417117 2-s2.0-84874126874 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84874126874&doi=10.1109%2fSMElec.2012.6417117&partnerID=40&md5=a8496493fb2de00c10232229a23d44f5 https://irepository.uniten.edu.my/handle/123456789/29515 6417117 173 176 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	high-k/metal gate Scaling down ratio Silvaco Leakage currents Silicides Tungsten Design and simulation Design simulations Down-scaling Electrical characterization Fabrication tool Gate length Metal gate NMOS transistors Optimal values Scale down Scaling down Silvaco TiO Tungsten silicide Titanium dioxide
spellingShingle	high-k/metal gate Scaling down ratio Silvaco Leakage currents Silicides Tungsten Design and simulation Design simulations Down-scaling Electrical characterization Fabrication tool Gate length Metal gate NMOS transistors Optimal values Scale down Scaling down Silvaco TiO Tungsten silicide Titanium dioxide Afifah Maheran A.H. Menon P.S. Ahmad I. Elgomati H.A. Majlis B.Y. Salehuddin F. Scaling down of the 32 nm to 22 nm gate length NMOS transistor
description	In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. � 2012 IEEE.
author2	36570222300
author_facet	36570222300 Afifah Maheran A.H. Menon P.S. Ahmad I. Elgomati H.A. Majlis B.Y. Salehuddin F.
format	Conference paper
author	Afifah Maheran A.H. Menon P.S. Ahmad I. Elgomati H.A. Majlis B.Y. Salehuddin F.
author_sort	Afifah Maheran A.H.
title	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_short	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_full	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_fullStr	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_full_unstemmed	Scaling down of the 32 nm to 22 nm gate length NMOS transistor
title_sort	scaling down of the 32 nm to 22 nm gate length nmos transistor
publishDate	2023
_version_	1811599155037995008
score	13.214268

Scaling down of the 32 nm to 22 nm gate length NMOS transistor

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