Analysis on optimizing the design of low power dynamic latch comparators

• Main Authors: Marufuzzaman M., Rahman L.F., Mutalib N., Sidek L.M., Alam L.
• Other Authors: 57205234835
• Format: Article
• Published: Alpha Publishers 2023

Comparator is a key component in energy-efficient applications such as memory-sensing, radiofrequency identification (RFID), analog-to-digital converter (ADC), etc. Among different types of comparator circuits, the preamplifier-based design is lack of increasing the power consumption due to large current. Moreover, dynamic latch comparators can provide high speed, low offset and high resolution, which makes it highly in demand compared to other comparators schemes. Additionally, the circuit can reduce the power dissipation due to its simple latch circuitry. Therefore, the design optimization of the comparator is a key research area in energy efficiency. Among various comparator circuit existed, the Dynamic Latch Comparators (DLCs) are more power efficient as it removes the usage of preamplifiers. Another important feature in optimizing the DLC circuit is the circuit complexity, rapidity, resolution and low-offset voltage. A very efficient and robust comparator design lead the researchers to analyze various parameters such as propagation delay, technology, power consumption, speed and offset for different types of the comparator. This review paper presents the comparative study between several types of DLCs and the methodologies used in designing optimized latch comparators. Major parameters such as low power and low supply voltages, propagation delay, input offset voltages as well as the techniques are compared among various recently published research works. The results and discussion among the comparison results will act as a design optimization guideline for future researchers especially in the optimization of DLCs. � 2020 Alpha Publishers. All rights reserved.