Implementation of PRINCE algorithm in FPGA
Algorithms; Application programs; Cryptography; Field programmable gate arrays (FPGA); Hardware; Hardware security; High speed cameras; Integrated circuit design; Logic Synthesis; Security of data; Throughput; Architectural modeling; Block ciphers; Cryptographic algorithms; Hardware implementations;...
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Institute of Electrical and Electronics Engineers Inc.
2023
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my.uniten.dspace-223982023-05-29T14:00:44Z Implementation of PRINCE algorithm in FPGA Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. Tariq B. 56417806700 6508169028 36682671900 24726154700 16246214600 57193327622 Algorithms; Application programs; Cryptography; Field programmable gate arrays (FPGA); Hardware; Hardware security; High speed cameras; Integrated circuit design; Logic Synthesis; Security of data; Throughput; Architectural modeling; Block ciphers; Cryptographic algorithms; Hardware implementations; PRINCE; Software implementation; Very high speed integrated circuits; VHDL; Computer hardware description languages This paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows an encryption block data of 64 bits within one clock cycle, reducing the hardware area and producing a high throughput and low latency. It also showed high speed processing and consumed low power. To do this, firstly, the encryption, decryption and key schedule are all implemented with small hardware resources, Next, an efficient hardware architectural model for PRINCE algorithms was developed using very high speed integrated circuit hardware description language (VHDL). Finally, the VHDL design for PRINCE algorithm was synthesized in FPGA boards. Two FPGA boards were used in this study, which are Virtex-4 and Virtex-6. The results show a throughput of 2.03 Gbps and efficiency of 2.126 Mbps/slice for Virtex-4, whereas a throughput of 4.18 Gbps and efficiency of 8.681 Mbps/slice for Virtex-6. � 2014 IEEE. Final 2023-05-29T06:00:44Z 2023-05-29T06:00:44Z 2015 Conference Paper 10.1109/ICIMU.2014.7066593 2-s2.0-84937405931 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84937405931&doi=10.1109%2fICIMU.2014.7066593&partnerID=40&md5=91d5c300f5f56df56c00e9c09a3005e8 https://irepository.uniten.edu.my/handle/123456789/22398 7066593 1 4 Institute of Electrical and Electronics Engineers Inc. Scopus |
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| description |
Algorithms; Application programs; Cryptography; Field programmable gate arrays (FPGA); Hardware; Hardware security; High speed cameras; Integrated circuit design; Logic Synthesis; Security of data; Throughput; Architectural modeling; Block ciphers; Cryptographic algorithms; Hardware implementations; PRINCE; Software implementation; Very high speed integrated circuits; VHDL; Computer hardware description languages |
| author2 |
56417806700 |
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56417806700 Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. Tariq B. |
| format |
Conference Paper |
| author |
Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. Tariq B. |
| spellingShingle |
Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. Tariq B. Implementation of PRINCE algorithm in FPGA |
| author_sort |
Abbas Y.A. |
| title |
Implementation of PRINCE algorithm in FPGA |
| title_short |
Implementation of PRINCE algorithm in FPGA |
| title_full |
Implementation of PRINCE algorithm in FPGA |
| title_fullStr |
Implementation of PRINCE algorithm in FPGA |
| title_full_unstemmed |
Implementation of PRINCE algorithm in FPGA |
| title_sort |
implementation of prince algorithm in fpga |
| publisher |
Institute of Electrical and Electronics Engineers Inc. |
| publishDate |
2023 |
| _version_ |
1806423398168920064 |
| score |
13.214268 |