FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation
Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (...
Saved in:
Main Authors: | , |
---|---|
Format: | Article |
Language: | English |
Published: |
Petanika Journal
2022
|
Subjects: | |
Online Access: | http://ir.unimas.my/id/eprint/37826/1/implementation1.pdf http://ir.unimas.my/id/eprint/37826/ http://www.pertanika.upm.edu.my/pjst/browse/regular-issue?article=JST-2895-2021 https://doi.org/10.47836/pjst.30.1.32 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
id |
my.unimas.ir.37826 |
---|---|
record_format |
eprints |
spelling |
my.unimas.ir.378262022-02-03T07:02:51Z http://ir.unimas.my/id/eprint/37826/ FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation Shamsiah, Suhaili Norhuzaimin, Julai TK Electrical engineering. Electronics Nuclear engineering Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA- 256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA- 256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design. Petanika Journal 2022-01-01 Article PeerReviewed text en http://ir.unimas.my/id/eprint/37826/1/implementation1.pdf Shamsiah, Suhaili and Norhuzaimin, Julai (2022) FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation. Petanika Journal Science & Technology, 30 (1). pp. 581-603. ISSN 0128-7680 http://www.pertanika.upm.edu.my/pjst/browse/regular-issue?article=JST-2895-2021 https://doi.org/10.47836/pjst.30.1.32 |
institution |
Universiti Malaysia Sarawak |
building |
Centre for Academic Information Services (CAIS) |
collection |
Institutional Repository |
continent |
Asia |
country |
Malaysia |
content_provider |
Universiti Malaysia Sarawak |
content_source |
UNIMAS Institutional Repository |
url_provider |
http://ir.unimas.my/ |
language |
English |
topic |
TK Electrical engineering. Electronics Nuclear engineering |
spellingShingle |
TK Electrical engineering. Electronics Nuclear engineering Shamsiah, Suhaili Norhuzaimin, Julai FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation |
description |
Security has grown in importance as a study issue in recent years. Several cryptographic
algorithms have been created to increase the performance of these information-protecting
methods. One of the cryptography categories is a hash function. This paper proposes the
implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding
transformation approach was presented in this study to enhance the throughput of the SHA-
256 design. The unfolding method is employed in the hash function by producing the hash
value output based on modifying the SHA-256 structure. In this unfolding method, SHA-
256 decreases the number of clock cycles required for traditional architecture by a factor of
two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256
design can generate up to four parallel inputs for the output. As a result, the throughput of the
SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim
was used to validate the output simulations created in Verilog code. The SHA-256 hash
function factor four hardware implementation was successfully tested using the Altera
DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding
hash function with factor four provides the most significant throughput of around 4196.30
Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256
design in terms of maximum frequency. As a
result, the throughput of SHA-256 increases
13.7% compared to unfolding factor two and
58.1% improvement from the conventional
design of SHA-256 design. |
format |
Article |
author |
Shamsiah, Suhaili Norhuzaimin, Julai |
author_facet |
Shamsiah, Suhaili Norhuzaimin, Julai |
author_sort |
Shamsiah, Suhaili |
title |
FPGA-based Implementation of SHA-256 with Improvement of
Throughput using Unfolding Transformation |
title_short |
FPGA-based Implementation of SHA-256 with Improvement of
Throughput using Unfolding Transformation |
title_full |
FPGA-based Implementation of SHA-256 with Improvement of
Throughput using Unfolding Transformation |
title_fullStr |
FPGA-based Implementation of SHA-256 with Improvement of
Throughput using Unfolding Transformation |
title_full_unstemmed |
FPGA-based Implementation of SHA-256 with Improvement of
Throughput using Unfolding Transformation |
title_sort |
fpga-based implementation of sha-256 with improvement of
throughput using unfolding transformation |
publisher |
Petanika Journal |
publishDate |
2022 |
url |
http://ir.unimas.my/id/eprint/37826/1/implementation1.pdf http://ir.unimas.my/id/eprint/37826/ http://www.pertanika.upm.edu.my/pjst/browse/regular-issue?article=JST-2895-2021 https://doi.org/10.47836/pjst.30.1.32 |
_version_ |
1724078574874394624 |
score |
13.160551 |