Design of CMOS power amplier

• Main Author: Khoo, Kian Hua
• Format: Final Year Project Report
• Language: English; English
• Published: Universiti Malaysia Sarawak (UNIMAS) 2011
• Subjects: TA Engineering (General). Civil engineering (General)
• Online Access: http://ir.unimas.my/id/eprint/26358/1/Design%20of%20CMOS%20power%20amplier%2024pgs.pdf; http://ir.unimas.my/id/eprint/26358/4/Design%20of%20CMOS%20power%20amplier.pdf; http://ir.unimas.my/id/eprint/26358/

Power amplifier (PA) is an important component of wireless transceiver in communications system. PAuses radio frequency for transmissio n between mobile wireless infrastructures. Complementary Metal Oxide Semico nductor (CMOS) techno logy is being used for design o f system integration on chip in PA. This is due to its improved operation speed tlu·ough downsizing. Being the most power hungry component o f radio frequency (RF) front end, designing a high perio rmance power amplifier is one of the most challenging parts in the wire less transce iver. The performance o f power amp lifier can be detennined in terms of signal linea rity, output power, and power gain. A proposed PA is a single-ended class AB cascode CMOS power amplitier. The simulation too l used in this project is LTspice IY. The power amplifier is operated at 3 GHz with an input power of 8 dBm and a supply vo ltage of 3 volt This project is to design a RF CMOS power ampl ifier for mobil e communications.