Built in self test for RAM using VHDL

• Main Authors: Husin, M.H., Leong, S.Y., Sabri, M.F.M.
• Format: E-Article
• Language: English
• Published: IEEE 2013
• Subjects: TA Engineering (General). Civil engineering (General)
• Online Access: http://ir.unimas.my/id/eprint/16645/1/Built%20in%20self%20test%20for%20RAM%20Using%20VHDL.pdf; http://ir.unimas.my/id/eprint/16645/; http://ieeexplore.ieee.org/document/6504323/

This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Gen...